Power management design of the hottest PLL module

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Power management design of phase locked loop module


phase locked loop (PLL) is the basic building block of modern communication system. PLLs are usually used in radio receivers or transmitters, mainly providing "Lo" function; It can also be used for clock signal distribution and noise reduction, and is increasingly used as a clock source for high sampling rate analog-to-digital or digital to analog conversion

as the noise performance of each generation of PLL is improving, the impact of power supply noise becomes more and more obvious, and in some cases, the noise performance can be limited

this paper discusses the basic PLL scheme shown in Figure 1 and examines the power management requirements of each building block

figure 1 The transformation of the coal-fired furnace of the plastic granulator system based on various power management requirements has become an important issue to be solved urgently. In this PLL, the feedback control loop drives the voltage controlled oscillator (VCO), so that the oscillator frequency (or phase) accurately tracks the multiple of the applied reference frequency. Many excellent references (such as best PLL 1) explain the mathematical analysis of PLL; ADI's adisimpll and other simulation tools are very helpful to understand the loop transfer function and calculation. Let's take a look at the PLL building blocks in turn

vco and VCO push

the voltage controlled oscillator converts the error voltage from the phase detector to the output frequency. Device "gain" is defined as Kvco, which is usually expressed in mhz/v. Voltage controlled variable capacitance diodes (VCDs) are commonly used to regulate the frequency within a VCO. The gain of VCO is usually enough to provide sufficient frequency coverage, but it is still not enough to reduce the phase noise, because any varactor noise will be amplified by Kvco times, thereby increasing the output phase noise

the emergence of multi band integrated VCOs, such as the integrated VCOs for the frequency synthesizer ADF4350 that urgently need to be standardized in the market competition environment, can avoid the trade-off between Kvco and frequency coverage, so that PLL designers can use IC containing several medium gain VCOs and intelligent band switching program to select the appropriate band according to the programmed output frequency. This band division provides a wide overall range and low noise

in addition to switching from input voltage change to output frequency change (Kvco), power supply fluctuation will also bring interference to output frequency change. VCO sensitivity to power fluctuations is defined as VCO pushing, which is usually the required kvco A small part of. For example, kpushing is usually 5% to 20% of Kvco. Therefore, for high gain VCO, the boost effect increases, and the noise contribution of VCO power supply becomes more important

vco push voltage is measured by applying a DC tuning voltage to the VTune pin, changing the power supply voltage and measuring the frequency change. The crowd factor is the ratio of frequency change to voltage change, as shown in Table 1. ADF4350 PLL is used

reference 2 mentioned another method: coupling low-frequency square wave DC into the power supply, and observing the frequency shift keying (FSK) modulation peak on either side of the VCO spectrum (Fig. 2). The VCO push coefficient is obtained by dividing the frequency deviation between peaks by the square wave amplitude. This measurement method is more accurate than the static DC test because it eliminates any thermal effects associated with changes in DC input voltage. Figure 2 shows the spectrum analyzer curve when ADF4350 VCO output is at 3.3 GHz and a 10 kHz, 0.6 V P-P square wave is applied to the nominal 3.3 V power supply. For the crowd factor of 1.62 mhz/0.6 V or 2.7 mhz/v, the final deviation is 3326.51 MHz – 3324.89 MHz = 1.62 MHz. This result can be compared with the static measurement of 2.3 mhz/v in Table 1

figure f4350 VCO response spectrum analyzer curve to power supply modulation through 10kHz, 0.6V P-P square wave

in PLL system, higher VCO push means greater increase of VCO power supply noise. In order to minimize the impact on VCO phase noise, a low-noise power supply is required

references 3 and 4 provide examples of how different low dropout regulators (LDOS) affect PLL phase noise. For example, the literature compares the performance of adp3334 and ADP150 LDO when supplying power to ADF4350. The integrated RMS noise of adp334 regulator is 27 μ V (from 10 Hz to 100 kHz for more than 40 years). This result can be compared with 9 of LDO ADP150 used on ADF4350 evaluation board μ V comparison. The difference in the measured PLL phase noise spectral density can be seen in Figure 3. The measurement was carried out using a 4.4 GHz VCO frequency, where the VCO push is the maximum (Table 1), so it is the worst case result. ADP150 regulator noise is low enough that its contribution to VCO noise is negligible, which can be confirmed by repeated measurements using two AA batteries (assuming "no noise")

figure 3 Comparison of phase noise of ADF4350 at 4.4ghz when using adp3334 and adp150ldo to supply power to (AA battery)

Figure 3 emphasizes the importance of low-noise power supply for ADF4350, but what are the requirements for power supply or LDO noise

similar to VCO noise, the phase noise contribution of LDO can be regarded as the additive component LDO (T), as shown in Figure 4. Again, the VCO excess phase expression is used to obtain:


in the frequency domain, where vldo (f) is the voltage noise spectral density of LDO

Spectral density s of single sideband power supply within the bandwidth of

1 Hz Φ (f) The inspection and record can be obtained from the following formula:

when expressed in dB, the formula used to calculate the phase noise contribution caused by the power supply noise is as follows:

where l (LDO) is the noise contribution of the regulator to the VCO phase noise (expressed in dbc/hz) when the offset is f; f; Kpushing is the pushing coefficient of VCO, expressed in hz/v; Vldo (f) is the noise spectral density at a given frequency offset, expressed in v/√ Hz

figure 4 Small signal additive VCO power supply noise model

in free mode VCO, the total noise is lldo value plus VCO noise. If it is expressed in DB:

for example, try to consider a VCO with a push coefficient of 10 mhz/v and a phase noise of – 116 dbc/hz measured at 100 kHz offset: what is the power supply noise spectral density required to not reduce the VCO noise performance at 100 kHz? Power supply noise and VCO noise are added as square and root, so the power supply noise should be at least 6 dB lower than VCO noise in order to minimize the noise contribution. So lldo should be less than – 122 dbc/hz. Use formula 1,

to solve vldo (f),

under 100 kHz offset, vldo (f) = 11.2 nv/√

the LDO noise spectral density under a given offset can usually be read through the typical performance curve in the LDO data book

when the VCO is connected in the negative feedback PLL, the LDO noise passes through the PLL loop filter for high pass filtering in a manner similar to the VCO noise. Therefore, the above formula is only applicable to frequency offset greater than PLL loop bandwidth. Within the PLL loop bandwidth, PLL can successfully track and filter LDO noise, thus reducing its noise contribution

ldo filtering

to improve LDO noise, there are usually two options: use LDO with less noise, or post filter the LDO output. When the noise requirement without filter exceeds the capability of economical LDO, the filtering option may be a good choice. A simple LC π filter is usually sufficient to reduce out of band LDO noise by 20 dB (Fig. 5)

figure 5 LC π filter used to attenuate LDO noise

very careful device selection is required. The typical inductance is in the micro Henry range (ferrite core is used), so it is necessary to consider the saturation current (isat) specified in the inductance data book as the DC level when the inductance drops by 10%. The current consumed by VCO shall be less than isat The effective series resistance (ESR) is also a problem because it causes an IR voltage drop across the filter. For microwave VCOs that consume 300 Ma DC current, an inductance with ESR less than 0.33 Ω is required to generate an IR voltage drop less than 100 mV. The lower non-zero ESR can also suppress the filter response and improve the stability of LDO. For this reason, it may be practical to select a capacitor with very low parasitic ESR and add a special series resistor. The above scheme can be easily simulated in spice using a downloadable device evaluator such as Ni Multisim

charge pump and filter

charge pump converts the error voltage of phase detector into current pulse, which is integrated and smoothed by PLL loop filter. The charge pump can normally operate at a voltage up to 0.5 V below its supply voltage (VP). For example, if the maximum charge pump power supply is 5.5 V, the charge pump can only operate at the maximum 5 V output voltage. If the VCO requires a higher tuning voltage, an active filter is usually required. For useful information and reference design of the actual PLL, please refer to the circuit note cn-0174. For the way to deal with high voltage, please refer to the design of high performance PLL using high voltage VCO. "This article was published in Volume 43, issue 4 (2009) of the analog dialogue. The alternative of active filter is to use PLL and charge pump designed for higher voltage. For example, adf4150hv can work with charge pump voltage up to 30 V, thus eliminating active filter in many cases

the low power consumption of the charge pump makes it seem attractive. A boost converter can be used to generate a high charge pump voltage from a lower power supply voltage. However, the switching frequency ripple associated with such DC-DC converters may generate interference noise at the output of the VCO. High PLL spurious may cause the transmitter transmit shielding test to fail, or reduce the sensitivity and out of band blocking performance in the receiver system. To help guide the specification of the converter ripple, use the measurement settings in Figure 6 to obtain the relationship between the overall power suppression curve and frequency for various PLL loop bandwidths

figure 6 The ripple signal of charge pump power supply suppression setting

17.4 MV (– 22 DBM) is AC coupled to the power supply voltage and scanned within the frequency range. The stray level is measured at each frequency when the sample used for the chemical resistance test is immersed in the chemical for a period of time, and the PSR is calculated according to the difference between the – 22dbm input and the stray output level (expressed in DB). 0.1 left in place μ F and 1 NF charge pump power supply decoupling capacitors provide a certain attenuation for the coupling signal, so the signal level at the generator increases until 17.4 MV is directly measured on the pin at each frequency point. The results are shown in Figure 7

figure f4150hf charge pump power supply suppression curve

within the PLL loop bandwidth, the power supply suppression initially becomes worse as the frequency increases. As the frequency approaches the PLL loop bandwidth, the ripple frequency is attenuated in a manner similar to the reference noise, and the PSR is improved. This graph shows that a boost converter with a higher switching frequency (ideally greater than 1 MHz) is required to minimize switching spurious. In addition, PLL loop bandwidth should be minimized as far as possible


1.3 MHz, adp1613 is a suitable boost converter. If the PLL loop bandwidth is set to 10 kHz, the PSR may reach about 90 dB; When the loop bandwidth is 80 kHz, the PSR is 50 dB. First, after the PLL spurious level requirements are solved, the ripple level required for the output of the boost converter can be determined. For example, if the PLL requires spurious less than – 80 DBM and the PSR is 50 dB, the ripple power at the charge pump power input needs to be less than – 30 DBM, that is, 20 mV p-p. If enough decoupling capacitors are placed near the charge pump power supply pins, the ripple voltage at the above levels can be easily realized by using a ripple filter. For example, a 100 NF decoupling capacitor can provide more than 20 dB of ripple attenuation at 1.3mhz. Capacitors with appropriate voltage ratings should be used with care; For example, if the boost converter generates an 18 V power supply, a capacitor with a rating of 20V or higher should be used

use the Excel based design tool adp161x The design of boost converter and ripple filter can be simplified. Figure 8 shows the design for 5 V input to 20 V output

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